1. Field of the Invention
The present invention relates to an analog/digital (A/D) converting technique, and more particularly to an A/D converting circuit capable of minimizing a characteristic change of a cell array.
2. Description of the Conventional Art
Generally, an algorithmic A/D converter, a successive-approximation-register type A/D converter and a .SIGMA.-.DELTA. A/D converter are used in audio applications. Among those converters, the algorithmic A/D converter most effectively controls power consumption, clock speed, a number of devices thereof, etc. In particular, the algorithmic A/D converter, which is also called a cyclic or recirculating A/D converter, can be enlarged to a pipelined construction for a video signal process with slight modification of the A/D circuit block portion.
FIG. 1 is a block diagram showing a related art A/D converter. As shown in FIG. 1, the related art algorithmic A/D converter includes a switch 101 for selecting an input signal Vi or feedback signal Vf, a sample/hold amplifier 102 for sampling/holding a signal from the switch 101, and an A/D sub-converter 105 for converting an output signal from the sample/hold amplifier 102 to a digital signal. A D/A sub-converter 106 converts a signal outputted from the A/D sub-converter 105 to an analog signal and a subtracter 103 obtains a difference value by comparing signals outputted from each of the sample/hold amplifier 102 and the D/A sub-converter 106. A remain voltage amplifier 104 amplifies a signal outputted from the subtracter 103 at a predetermined level. A digital correcting unit 107 corrects an error of the output signal from the A/D sub-converter 105 by superimposing each single bit thereof and outputs an N bit digital signal that is corrected.
The operation of the related art A/D converter will now be described. First, when the switch 101 is connected to a channel 1 and an external analog signal Vi is inputted, the sample/hold amplifier 102 samples/holds the analog signal Vi. At this time, the n bit A/D sub-converter 105 converts the signal outputted from the sample/hold amplifier 102 to a digital signal, and the n bit D/A sub-converter 106 converts the digital signal from the A/D sub-converter 105 to an analog signal. The subtracter 103 generates a remain voltage, that is, a difference value between a signal from the sample/hold amplifier 102 and a signal from the D/A sub-converter 106, and the remain voltage amplifier 104 amplifies the remain voltage.
Then, the switch 101 is switched to channel 2 to connect an output terminal of the remaining voltage amplifier 104 to an input terminal of the sample/hold amplifier 102. Thus, the sample/hold amplifier 102 samples/holds a signal from the remain voltage amplifier 104.
Therefore, when the n bit A/D sub-converter 105 converts an error being held in the sample/hold amplifier 102 to a digital signal, the D/A sub-converter 106 converts the digital signal to an analog signal, and outputs the analog signal to the subtracter 103. The subtracter 103 subtracts the output signal from the A/D sub-converter 106 from an output signal from the sample/hold amplifier 102 and feeds back a resultant value to the sample/hold amplifier 102 via the remain voltage amplifier 104.
In the above-described operation, an n bit output signal is determined in each data conversion cycle, and the above operation is repeated until the digital correcting unit 107 outputs the N bit digital signal. The digital correcting unit 107 eliminates an offset or feedthrough error in the sample/hold amplifier 102, the A/D converter 105, and the D/A converter 106 by superimposing each data having n bits by 1 bit to output normal digital data.
However, the related art analog/digital converting circuit has various disadvantages. When a poly is not provided to a capacitance applied to the related art A/D converter circuit in a standard digital CMOS process such as a poly-poly or poly-diffusion, a new process is needed and should be applied. Further, in the related art, there is no method of minimizing power consumed in an analog circuit provided with an operational amplifier, etc. In addition, when a capacitance applied to the analog circuit significantly changes, the circuit operation becomes unstable.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.